LDOs are devices used to maintain a constant DC output voltage, designed to operate with a very small input-output voltage differential, and characterized by high-efficiency operation and low heat dissipation. ICs housing LDOs are used in many devices. For example, sources including such ICs can be found in wireless devices such as mobile terminals (e.g., cell phones, smartphones, etc.), digital media players (e.g., MP3s and MP4s), DVD players, portable PCs, tablets, etc.
As schematically illustrated in FIG. 1, the main components of an LDO 100 are (A) a power metal-oxide-semiconductor (MOS) transistor 110 connected between LDO input connector 120 (VIN) and LDO output connector 130 (VOUT), and (B) a differential amplifier (error amplifier) 140. Power MOS transistor 110 uses an electric field to control the shape and, hence, conductivity across the power MOS transistor's source and drain terminals. In other words, conductivity across the power MOS transistor is variable, depending on a signal applied on the power MOS transistor's gate terminal (hereinafter, the word “terminal” will be omitted for brevity).
One input 142 of differential amplifier 140 receives a feedback (i.e., a fraction thereof via feedback network G) from LDO output connector 130, and another input 144 of differential amplifier 140 receives a stable voltage reference (VOUT). Differential amplifier's output 146 is connected to power MOS transistor 110's gate to maintain constant output voltage (VOUT). If, for example, the output voltage (VOUT) rises too high relative to the reference voltage (VREF), the signal applied to power MOS transistor 110's gate changes to decrease conductivity, causing the output voltage (VOUT) to decrease.
LDOs may include a short circuit protection (SCP) arrangement that limits the current drawn from the LDO in case of accidental short circuit and avoids breakage of the chip. The SCP arrangement in FIG. 1 includes a small MOS transistor 150 having its source connected to LDO input connector 120 and its drain connected to a current mirror 155 (which is connected also to a current source 160), and to the ground (i.e., a fixed low voltage) via a resistor Rref.
A current Ismall flowing through small MOS transistor 150 is proportional to the output current Iout:Ismall−a·Iout  (1)where a is a proportionality factor of about 1/1000.
The SCP arrangement further includes an SCP differential amplifier 170 that compares a potential difference V determined by the product of Rref with a difference between the current flowing through small MOS transistor 150 and a reference current, Iref, supplied by current source 160 with a reference voltage VREF.V=Rref(a·Iout−Iref)  (2)
The SCP arrangement also includes a pull-up (Pup) MOS transistor 175 having its source connected to LDO input connector 120, its drain connected to small MOS transistor 150's gate, and its gate connected to the output of SCP differential amplifier 170. When a short circuit occurs at the output, output current Iout increases suddenly, causing the current flowing through small MOS transistor 150 to become too high relative to Iref. The SCP differential amplifier 170's output then decreases, causing Pup MOS transistor 175 to change voltage on power MOS transistor 110's gate, thereby preventing current from flowing there-through (i.e., closing power MOS transistor 110). Pup MOS transistor 175 is designed to have enough current capability to force (via small MOS transistor 150) power MOS transistor 110's gate to rise to VIN regardless the state of differential amplifier 140. Thus, small MOS transistor 150 and power MOS transistor 110 operate as a power sense structure. Typically, power MOS transistor 110, small MOS transistor 150 and Pup MOS transistor 175 are P-MOS transistors.
The SCP arrangement limits the LDO's output current Iout to a value Imax:
                              I                      ma            ⁢                                                  ⁢            x                          =                                            1              a                        ·                          (                                                I                  ref                                +                                                      V                    ref                                    /                                      R                    ref                                                              )                                =                                    1              a                        ⁢                                          I                                  ref                  ⁢                                                                          ⁢                  0                                            .                                                          (        3        )            
LDOs need an external output capacitor to be stable. Absence of the external output capacitor causes the LDO to oscillate, which is undesirable or even unacceptable. Although an IC with LDO may include a capless circuit enabling it to overcome the absence of the external output capacitor, presence of the external output capacitor must be determined to operate the LDO.
Conventionally, whether the external output capacitor is present is detected by independent circuitry, outside the IC housing the LDO. One conventional solution is to detect the presence of the external output capacitor by evaluating the discharge time of the external capacitor with an ADC. This solution requires (besides the ADC) a dedicated state machine to output an indication regarding the presence of the external output capacitor. The operation of the device including the IC housing the LDO must then have a dedicated detection timeslot during which the LDO cannot be used (its output voltage is 0). These constraints and additional equipment renders the conventional solution inefficient.
Accordingly, it is desirable to provide an IC housing an LDO which would efficiently incorporate external output capacitor detection while also providing short circuit protection.